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System Interfaces
MDS CMC J9
MDS CMC J6, J7, J8
PDK CMC J2
PDK CMC J5
PDK CMC J3
MII
MII
RMII
TDM
Rx
PORESET
Boot
TDM
Mode
Local Bus
RMII
Tx
LED
CPLD
Buffer
CPU Bus
VIA VT6510B
Ethernet Switch
I 2 C EEPROM
8
16
RMII
RMII
2
2
I 2 C
EEPROM
4x
HRESET
HDI16
R MII
RMII
MSC711x
MSC711x
MSC711x
MSC711x
LED
16
LED
16
LED
16
LED
16
16 MB DDR
SDRAM
16 MB DDR
SDRAM
16 MB DDR
SDRAM
16 MB DDR
SDRAM
Figure 3. Block Diagram of SPT711xPFCE
2.1
External Bus Through Programmable Logic
A complex programmable logic device (CPLD) converts bus transfers on the CMC connectors to HDI16,
Ethernet switch, or CPLD register transfers. This logic decodes the address and asserts the proper
chip-select signal when the PFC chip-select signal is asserted. The host device must meet the timing
requirements for the MSC711x HDI16, Ethernet switch, and CPLD register transfers, assuming a 10 ns
delay through the CPLD. Figure 4 shows the timing requirements for the Ethernet switch, which is the
slowest interface and therefore the driving influence on timing considerations. The actual value of timing
requirements is implementation-specific. Review all device specifications to determine the values.
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
Freescale Semiconductor
5
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